In recent years, both Networks-on-Chip, as an architectural solution for high-speed interconnect, and power consumption, as a key design constraint, have continued to gain interest in the design and research communities. This book offers a single-source reference to some of the most important design techniques proposed in the context of low-power design for networks-on-chip architectures.
- ISBN: 978-1-4899-9437-0
- Editorial: Springer
- Encuadernacion: Rústica
- Fecha Publicación: 20/11/2014
- Nº Volúmenes: 1
- Idioma: Inglés