Improve design efficiency and reduce costs with this practical guide to formal and simulation-based functional verification. Giving you a theoretical and practical understanding of the key issues involved, expert authors including Wayne Wolf and Dan Gajski explain both formal techniques (model checking, equivalence checking) and simulation-based techniques (coverage metrics, test generation). You get insights into practical issues including hardware verification languages (HVLs) and system-level debugging. The foundations of formal and simulation-based techniques are covered too, as are more recent research advancesincluding transaction-level modeling and assertion-based verification, plus the theoretical underpinnings of verification, including the use of decision diagrams and Boolean satisfiability (SAT). INDICE: 1. Model checking and equivalence checking M. Fujita; 2. Transaction level system modeling D. Gajski and S. Abdi; 3. Result checking, monitors and assertions H. Foster; 4. System debugging strategies W. Wolf; 5. Test generation and coverage metrics M. Sonza Reorda, G. Squillero and E. Sanchez; 6. System C and Vera in a verification flow S. Verma and I. G. Harris; 7. Decision diagrams for verification M. Ciesielski, D. K. Pradhan and A. M. Jabir; 8. Boolean satisfiability and EDA applications J. Marques-Silva.
- ISBN: 978-0-521-85972-1
- Editorial: Cambridge University Press
- Encuadernacion: Cartoné
- Páginas: 276
- Fecha Publicación: 01/01/2009
- Nº Volúmenes: 1
- Idioma: Inglés